1. Field of the Invention
The present invention relates to a dual damascene process of a semiconductor process. More particularly, the present invention relates to a dual damascene partial gap fill polymer fabrication process.
2. Description of the Related Art
In the fabrication of metal interconnects, damascene processes first form a trench and a via in the dielectric layer and then the trench and the via is filled with metal, in order to form a metal line and a plug. This method is used especially on metal that is difficult to etch. The dual damascene process is a method that forms both a metal line and plug simultaneously. That is to say, a trench and via are formed in the dielectric layer and the trench and via are filled simultaneously to form a metal line and plug. Among various dual damascene fabrication processes, a method exists wherein a via is formed and then a trench is formed. This process is known as the “via first dual damascene process”. The steps of this conventional process are outlined below. As shown in 1A, a substrate 100 is provided. Metal layer 100 has already been formed on substrate 100 provided. Silicon nitride passivation layer 120, silicon oxide layer 130, etching stop layer 140, which is composed of silicon material, and silicon oxide layer 150 are formed sequentially over metal layer 110. Silicon oxide layer 150, etching stop layer 140, and silicon oxide layer 130 are sequentially patterned to form a via hole 160. Via hole 160 exposes a part of silicon nitride passivation layer 120.
As shown in FIG. 1B, photoresist layer 170 is formed over silicon oxide layer 150 and fills via hole 160 (the filled state is not shown). A lithographic process is conducted to pattern photoresist layer 170, in order to form trench 180 in photoresist layer 170. Trench 180 exposes via hole 160.
As shown in FIG. 1C, using photoresist layer 170 as a mask, silicon oxide layer 150 is etched until etching stop layer 140 is exposed, to form trench 190 in silicon oxide layer 150. Photoresist layer 170 and silicon nitride passivation layer 120 at the bottom of via hole 160 is removed to expose a portion of metal layer 110, which allows the plug, formed in a later step and the metal layer to be connected.
However, as the dimensions of electrical devices continues to decrease, the conventional via first dual damascene causes the problem of fencing to emerge. This problem is described below. As shown in FIG. 1B, the aspect ratio of via hole 160 increases as device size decreases. As a result, photoresist layer 170 remains on the bottom and inner walls of via hole 160, after lithography has been conducted. As shown in fig IC, when silicon oxide layer 150 is etched to form trench 190, photoresist layer 170 remaining on the inner walls of via hole 160 obstruct the etching of the periphery of silicon oxide layer 150. As a result, fencing 150a occurs around the edge of via hole 160. Fencing obstructs the filling of metal into depressed region 199 as shown in FIG. 1C. Moreover, fencing reduces the cross sectional area of the conductive line formed in a subsequent step.
A dual damascene partial gap fill polymer fabrication process has been proposed to resolve the problem of fencing caused by the inability to completely remove photoresist layer from the via hole. The steps of this conventional method are outlined below.
As shown in FIG. 2A, substrate 200 having metal layer 210 is provided. Silicon nitride passivation layer 220, silicon oxide layer 230, etching stop layer 240 composed of silicon nitride material and silicon oxide layer 250 are formed sequentially on substrate 200. Silicon oxide layer 250, etching stop layer 240, and silicon oxide layer 230 are patterned sequentially, to form via hole 260 which exposes a portion of silicon nitride passivation layer 220. Via hole 260 is then filled with partial gap fill polymer 262.
As shown in FIG. 2B, silicon oxide layer 250 is covered by photoresist layer 270, which also fills trench 260 (filled state not shown). A lithographic process is conducted to pattern photoresist layer 270, to form trench 280. Because via hole 260 has already been filled with partial gap fill polymer 262, photoresist layer 270 in via hole 260 is shallow. Thus, photoresist layer 270 can be completely removed during the lithographic process.
As shown in FIG. 2C, using photoresist layer 270 as a mask, silicon oxide layer 250 is etched until etching stop layer 240 is exposed. Photoresist layer 270 and partial fill gap polymer 262 are removed. Passivation layer 220 on the bottom portion of via hole 260 is removed, to expose a portion of metal layer 210 allowing the plug formed in a later step and metal layer 210 to be connected.
The conventional partial gap fill polymer process, however, can only be used with isolated via holes and, thus, cannot resolve the problem of fencing associated with dense via holes. The reason lies in the fact that the number of dense via holes within a unit of area is greater than the number of isolated via holes. Thus, when partial gap fill polymer is deposited, the portion of partial gap fill polymer in each dense via hole is much less. As a result, the height of the partial fill polymer within dense via holes is much lower. Consequently, the photoresist layer filling the dense via holes is deeper, which causes photoresist layer to remain on the inner walls of dense via holes after lithography and leads to fencing.